Method for etching dielectric films

ABSTRACT

A method for removing a plurality of dielectric films from a supporting substrate by providing a substrate with a second dielectric layer overlying a first dielectric layer, contacting the substrate at a first temperature with a first acid solution exhibiting a positive etch selectivity at the first temperature, and then contacting the substrate at a second temperature with a second acid solution exhibiting a positive etch selectivity at the second temperature. The first and second dielectric layers exhibit different etch rates in the first and second acid solutions. The first and second acid solutions may contain phosphoric acid. The first dielectric layer may be silicon nitride and the second dielectric layer may be silicon oxide. Under these conditions, the first temperature may be about 175° C. and the second temperature may be about 155° C.

CROSS-REFERENCE TO RELATED APPLICATIONS

[0001] This application is a continuation of application Ser. No.09/518,292, filed Mar. 3, 2000, now U.S. Pat. No. 6,497,827, issued Dec.24, 2002, which is a continuation of application Ser. No. 09/055,644,filed Apr. 6, 1998, now U.S. Pat. No. 6,117,351, issued Sep. 12, 2000.

BACKGROUND OF THE INVENTION

[0002] 1. Field of the Invention

[0003] This invention relates generally to the field of semiconductordesign and fabrication. Specifically, the invention relates to methodsfor removing dielectric layers from integrated circuit devices.

[0004] 2. State of the Art

[0005] During manufacture of integrated circuit (IC) devices, dielectriclayers are often used to aid the fabrication process. For example, toprotect active areas of a silicon substrate during formation of oxideisolation regions (e.g., field oxide regions), a silicon nitride layerwill be formed over the active areas of the substrate. While forming theoxide isolation regions, the surface of the silicon nitride layerbecomes oxidized. After aiding the fabrication process, the oxidizedsilicon nitride layer must be removed.

[0006] Several processes are known to remove oxidized silicon nitridelayers from IC devices. In one removal process, described in U.S. Pat.No. 3,709,749 and incorporated herein by reference, a substratecontaining the oxidized silicon nitride layer is dipped inhigh-temperature (100° C.) water. Other removal processes use phosphoricacid (H₃PO₄). See, for example, W. van Gelder et al., Journal of theElectrochemical Society: SOLID STATE SCIENCE, Vol. 114, No.8, pp.869-872 (August 1967), U.S. Pat. No. 4,092,211, and K. Sato et al.,Detailed Study of Silicon-Nitride-Etching Mechanism by Phosphoric Acidfor Advanced ULSI Processing (Abstract), Tohoku University (dateunknown), the disclosures of which are incorporated herein by reference.At low temperatures, phosphoric acid is unable to significantly etch thesilicon nitride because of its inability to appreciably attack thesilicon oxide. Higher temperatures speed up the attack of the siliconoxide, but decrease the etch rate of the silicon nitride. As a result,it has been difficult to etch an oxidized silicon nitride structureusing

[0007] In an attempt to increase the etch rate of silicon oxide at lowtemperatures, fluoroboric acid has been combined with phosphoric acid asdescribed in U.S. Pat. No. 3,859,222, incorporated herein by reference.But adding fluoroboric acid has not significantly improved the abilityof phosphoric acid to etch the oxidized silicon nitride structurewithout also attacking and degrading the oxide isolation regions.

[0008] Hydrofluoric (HF) acid has also been employed to etch oxidizedsilicon nitride structures. Unfortunately, the selectivity of HF acid isnegative, or, in other words, HF acid severely etches silicon oxide tothe extent of removing silicon oxide at a rate faster than siliconnitride, producing unfavorable geometry for further IC deviceprocessing. When a field oxide region is present, the negative etchselectivity removes large amounts of the field oxide region, thusimpairing the ability of the field oxide to act as an isolating region.

[0009] Another removal process uses HF acid in a first step andphosphoric acid in a second step to etch oxidized silicon nitridestructures. See U.S. Pat. No. 3,657,030, incorporated herein byreference. The HF acid etches off enough of the oxide surface to enablethe phosphoric acid to attack the silicon nitride. Too little removal bythe HF acid prevents the phosphoric acid from attacking the siliconnitride, while too much removal by the HF acid unduly depletes the oxideisolation regions. Etching with HF acid followed by phosphoric acid,however, also increases the materials used—each HF and H₃PO₄ etchingstep is followed by a rinsing step, thus increasing the complexity andcost of the fabrication process.

SUMMARY OF THE INVENTION

[0010] The present invention provides a method of removing an oxidizedsilicon nitride layer from an IC device once it has served its purposeduring fabrication. While removing the oxidized silicon nitride layer,the inventive method minimizes removal of desired isolation regions fromthe IC device. The method uses a two step process: one step to removethe oxidized portion of the oxidized silicon nitride layer; and a secondstep to remove the silicon nitride portion of the oxidized siliconnitride layer. In removing the oxidized silicon nitride layer, themethod uses an acid solution exhibiting a positive etch selectivity, orability to etch one material (i.e., silicon nitride) faster than asecond material (i.e., silicon oxide).

[0011] The present invention includes a method for removing a pluralityof dielectric films from a supporting substrate by providing a substratewith a second dielectric layer overlying a first dielectric layer,contacting the substrate at a first temperature with a first acidsolution exhibiting a positive etch selectivity with respect to thesecond dielectric layer at the first temperature, and then contactingthe substrate at a second temperature with a second acid solutionexhibiting a positive etch selectivity with respect to the firstdielectric layer at the second temperature. The first and second acidsolutions preferably contain phosphoric acid. The first and seconddielectric layers exhibit different etch rates in the first acidsolution and the second acid solution. The first dielectric layer ispreferably silicon nitride and the second dielectric layer is preferablysilicon oxide. The second temperature is preferably lower than the firsttemperature.

[0012] The present invention yields several advantages over the priorart. One advantage is that the etch selectivity for siliconoxide-silicon nitride composite structures is improved, resulting inbetter geometry for further IC device processing. Another advantage, atleast when the same acid is used as the first and the second etchant, isthat the complexity and cost of the manufacturing process decreasesbecause less wafer processing is necessary, i.e., separate rinsing anddrying steps are not required.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWINGS

[0013] The present invention is illustrated in the accompanying drawingsin which:

[0014] FIGS. 1-2, 3 a, 3 b, and 4-5 comprise cross-sectional views in aprocess of removing a plurality of dielectric layers from a supportingsubstrate according to the present invention; and

[0015]FIG. 6 comprises a cross-sectional view of an apparatus used inremoving a plurality of dielectric layers from a supporting substrateaccording to the present invention.

DETAILED DESCRIPTION OF THE INVENTION

[0016] The present invention provides a process for removing dielectriclayers during IC and semiconductor device fabrication. In particular,the present invention includes a process for removing silicon nitrideand silicon oxide layers from an IC device using a phosphoric acidsolution.

[0017] The following disclosure provides specific details, such asmaterial thicknesses and types, to thoroughly describe the presentinvention. The skilled artisan, however, would understand that thepresent invention may be practiced without employing these specificdetails. Indeed, the present invention can be practiced in conjunctionwith conventional fabrication techniques in the industry.

[0018] The process steps described below do not form a complete processflow for manufacturing IC devices. Only the process steps necessary tounderstand the present invention are disclosed.

[0019] As shown in FIG. 1, protecting layer 3 is first provided oversubstrate 2, with dielectric layer 6 provided over protecting layer 3.The substrate may be any surface suitable for IC device formationincluding ceramic, glass, or semiconductor wafers. The surface of thesubstrate may contain individual devices, such as transistors orcapacitors, or intermediate layers, such as metal layers or dielectriclayers. Preferably, substrate 2 comprises a silicon surface, such as asilicon wafer or bulk silicon region. Exemplary bulk silicon regionsinclude silicon-on-insulator or silicon-on-sapphire structures.

[0020] Protecting layer 3 serves to reduce tensile stress betweensubstrate 2 and first dielectric layer 6. Accordingly, protecting layer3 may comprise any material exhibiting such a property, like siliconoxide. Preferably, the protecting layer is a thermal silicon oxidelayer, often referred to as a “pad” oxide.

[0021] Dielectric layer 6 may be any dielectric layer used inmanufacturing IC devices, such as doped or undoped silicon oxide,silicon nitride, organic dielectrics, or other electrically insulatingmaterials, or multiple layers of these materials. Preferably, dielectriclayer 6 is silicon nitride, including silicon nitride not containing astoichiometric amount of silicon or nitrogen. The silicon nitride mayoptionally contain varying amounts of oxygen and/or hydrogen.

[0022] Dielectric layer 6 is deposited or otherwise formed overprotecting layer 3 by any process yielding the desired physical andchemical characteristics. Processes for forming the preferred siliconnitride layer include chemical vapor deposition (CVD) processes, such ashigh-temperature CVD processes, plasma-enhanced CVD processes, or lowpressure CVD processes, in an atmosphere with a gas or mixture of gasescontaining silicon and nitrogen.

[0023] As illustrated in FIG. 2, portions of dielectric layer 6 andprotecting layer 3 are next removed. The portions of these layersremaining on substrate 2 overlie active areas of the substrate, i.e.,areas in which transistors and other devices will be built. Any processwhich removes portions of protecting layer 3 and dielectric layer 6without degrading substrate 2 can be used. Preferably, the portions ofthese two layers are removed by spinning a photoresist layer ondielectric layer 6, exposing and developing the photoresist layer toexpose portions of dielectric layer 6, etching the exposed portions ofdielectric layer 6 and underlying portions of protecting layer 3 (ifnecessary, using dielectric layer 6 as a mask), and then removing anyphotoresist remaining on dielectric layer 6.

[0024] Next, as shown in FIG. 3a, isolation regions 4 are formed insubstrate 2. Any process forming regions isolating the actives areas ofsubstrate 2 can be used to form isolation regions 4, such as thermaloxidation. Exemplary isolation regions include field oxide regions andisolation regions formed by a trench and refill process. Preferably,isolation regions 4 are field oxide regions formed by thermallyoxidizing substrate 2.

[0025] While substrate 2 is being thermally oxidized, dielectric layer 6is partially oxidized, especially when dielectric layer 6 is siliconnitride, thus forming oxidized surface layer 8. Oxidized surface layer 8will vary in thickness depending on the temperature and duration of theprocess forming isolation regions 4. When dielectric layer 6 is siliconnitride, the surface of oxidized surface layer 8 is essentiallynitrogen-free oxide. At increased depths of oxidized surface layer 8,the oxygen content decreases and the nitrogen content increases untilreaching the silicon nitride layer. Thus, a silicon oxynitride filmexists between oxidized surface layer 8 and the underlying dielectriclayer 6 where Si, O, and N are all present.

[0026] Oxidized surface layer 8 exhibits an etch rate different thandielectric layer 6 when exposed to the same etchant, as explained below.Preferably, oxidized surface layer 8 is a thermal silicon oxide layer,including a silicon oxide layer not containing a stoichiometric amountof silicon or oxygen. The silicon oxide may contain varying amounts ofhydrogen and/or nitrogen, as explained above.

[0027] As depicted in FIG. 3b, oxidized surface layer 8 optionally hasinsulating layer 10 disposed thereon. When isolation regions 4 areformed by a trench and refill process, a trench is made in substrate 2where isolation regions 4 will be formed. Prior to depositing the refillinsulating material, the substrate is thermally oxidized, thus formingoxidized surface layer 8 on dielectric layer 6 and in the trench.Subsequently, insulating material for isolation regions 4 is depositedin the trench and on oxidized surface layer 8, thus forming insulatinglayer 10. Suitable insulating materials for these types of isolationregions include deposited silicon oxides such as BPSG oxides, silaneoxides, TEOS oxides, LPTEOS oxides, PETEOS oxides, or HDPTEOS oxides, orthe like.

[0028] After forming the composite structure of dielectric layer 6 andoxidized surface layer 8 (and optional insulating layer 10) onsupporting substrate 2, the resulting structure is contacted with afirst etchant. In one embodiment, the first etchant is an acid solutioncapable of removing dielectric layer 6, oxidized surface layer 8, and,when present, optional insulating layer 10. The acid solution, however,will not etch dielectric layer 6 and oxidized surface layer 8 at thesame rate, but must exhibit a positive etch selectivity. A positive etchselectivity means that the acid solution etches dielectric layer 6(e.g., silicon nitride) at a faster rate than oxidized surface layer 8.Preferably, the acid solution employed contains phosphoric acid. Theacid solution may contain any concentration of phosphoric acid in water,provided the acid solution exhibits a positive etch selectivity.Preferably, the phosphoric acid concentration ranges from about 50 toabout 100%, and is more preferably 85%. The phosphoric acid solution mayoptionally contain additional agents, such as buffering agents and/orother acids like fluoboric acid and sulfuric acid.

[0029] The first etchant, which is at a first temperature, removesinsulating layer 10 (when present) and a portion of oxidized surfacelayer 8. The first temperature is selected so the first etchant or acidsolution exhibits a positive etch selectivity. The first etchant andfirst temperature should be selected to obtain the highest etch ratepossible without detracting from the desired positive etch selectivity.When a phosphoric acid solution is employed as the first etchant, thefirst temperature is greater than 165° C. and preferably should rangefrom about 165° C. to about 220° C. More preferably, under theseconditions, the first temperature is about 175° C.

[0030] As shown in FIG. 4, after breaching the surface oxide andoxynitride portions of oxidized surface layer 8 (leaving a remainingportion 8′ of oxidized surface layer as shown in FIG. 4), and preferablyafter removing a substantial portion of this layer, the resultingstructure is contacted with a second etchant to remove a portion ofdielectric layer 6. Preferably, the remaining portion of oxidizedsurface layer 8 and a substantial portion of dielectric layer 6 areremoved. More preferably, as shown in FIG. 5, the remaining portion ofoxidized surface layer 8 and substantially all of dielectric layer 6 areremoved. The second etchant employed is an acid solution capable ofremoving both oxidized surface layer 8 and dielectric layer 6, and maybe the same or different than the first etchant. The acid solutionemployed as the second etchant must also exhibit a positive etchselectivity. Preferably, the acid solution employed contains phosphoricacid. The acid solution may contain any concentration of phosphoric acidin water, provided the acid solution exhibits a positive etchselectivity. Preferably, the phosphoric acid concentration ranges fromabout 50% to about 100%, and is more preferably 85%. The phosphoric acidsolution may contain additional agents, such as buffering agents andother acids like fluoboric acid and sulfuric acid.

[0031] The second etchant is held at a second temperature. The secondtemperature is selected so that the second etchant or acid solutionexhibits a positive etch selectivity. The second etchant and secondtemperature should be selected to obtain the highest etch rate possiblewithout detracting from the desired positive etch selectivity. When aphosphoric acid solution etch is employed as the second etchant, thesecond temperature is lower than the first temperature. The secondtemperature is less than 165° C., and preferably ranges from about 145°C. to about 165° C. More preferably, under these conditions, the secondtemperature is about 155° C.

[0032] The above process may be performed in any apparatus capable ofmaintaining the operating conditions described above, such as theapparatus illustrated in FIG. 6. In one embodiment, the first and secondremoval steps performed by the first and second etchants can beperformed in separate chambers. In this embodiment, the first removalstep could be performed at the first temperature in a first chamber (orbath) 20. The second removal process could then be performed in a secondbath or chamber 30 maintained at the second temperature. In anotherembodiment, where the same acid solution is used as both the first andsecond etchant, the process of the present invention can be performed inthe same chamber 20. In this embodiment, the first removal process canbe performed in chamber 20 at a first temperature. After the firstremoval process is complete, the temperature in chamber 20 can belowered and the second removal process performed without moving thesubstrate into chamber 30. However, when both removal steps areperformed in the same chamber, contaminants remaining from the firstremoval process can hinder the second removal process. Accordingly, thefirst and second removal steps are preferably carried out in separatechambers.

[0033] The present invention can be illustrated by the followingExample, which should not be viewed as limiting the present invention inany manner.

EXAMPLE

[0034] The preferred inventive method of using phosphoric acid at afirst, higher temperature in a first step and then at a second, lowertemperature in a second step was compared with using a conventionalmethod of using HF acid in a first step and then using phosphoric acidin a second step. In both instances, after forming a thin pad oxidelayer on a silicon substrate, a silicon nitride layer was deposited onthe pad oxide layer. The silicon nitride and pad oxide layers were thenpatterned and etched. Field oxide regions with a thickness of 2200angstroms were then formed by thermal oxidation in the substrate, alsothermally oxidizing the silicon nitride layer.

[0035] The oxidized surface layer and underlying silicon nitride layerwere then removed. Using the conventional HF acid in a first step andphosphoric acid in a second step to remove the oxidized surface layerand underlying silicon nitride layer resulted in about 240-260 angstromsof the field oxide regions also being removed. However, using theinventive method of phosphoric acid at 175° C. in a first step and thenphosphoric acid at 155° C. in a second step to remove the oxidizedsurface layer and underlying silicon nitride layer resulted in a fieldoxide loss of less than 80 angstroms.

[0036] While the preferred embodiments of the present invention havebeen described above, the invention defined by the appended claims isnot to be limited by particular details set forth in the abovedescription, as many apparent variations thereof are possible withoutdeparting from the spirit or scope thereof.

What is claimed is:
 1. A method for removing, from a semiconductorsubstrate, a silicon oxide gradient layer, said method comprising:providing a substrate bearing: a dielectric layer comprising a siliconoxide gradient sublayer having a maximum oxygen atom concentration at asurface thereof, said oxygen atom concentration decreasing monotonicallyto substantially zero with distance of material in said dielectric layerfrom an active surface of said substrate, the balance of said dielectriclayer comprising silicon nitride; contacting said surface with an acidsolution comprising phosphoric acid at a first temperature, said acidsolution at said first temperature exhibiting a positive etchselectivity for silicon oxide over silicon nitride; and graduallylowering a temperature of said acid solution to a second temperature,said acid solution at said second temperature exhibiting a positive etchselectivity for silicon nitride over a material of an adjacent layer orstructure.
 2. The method according to claim 1, wherein said providingsaid substrate comprises providing a substrate with said dielectriclayer comprising an exposed insulating layer.
 3. The method according toclaim 2, wherein said providing said substrate comprises providing saidsubstrate with said exposed insulating layer comprising at least one ofa BPSG oxide, a silane oxide, a TEOS oxide, an LPTEOS oxide, a PETEOSoxide, and an HDPTEOS oxide.
 4. The method according to claim 1, whereinsaid providing said substrate comprises providing a substrate with a padoxide layer beneath at least a portion of said dielectric layer.
 5. Themethod according to claim 1, wherein said contacting is effected withsaid first temperature being greater than about 165° C.
 6. The methodaccording to claim 1, wherein said contacting is effected with saidfirst temperature being about 165° C. to about 220° C.
 7. The methodaccording to claim 1, wherein said contacting is effected with saidfirst temperature being about 175° C.
 8. The method according to claim1, wherein said contacting is effected with said second temperaturebeing less than about 165° C.
 9. The method according to claim 1,wherein said contacting is effected with said second temperature beingabout 145° C. to about 165° C.
 10. The method according to claim 1,wherein said contacting is effected with said second temperature beingabout 155° C.
 11. The method according to claim 1, wherein saidcontacting comprises contacting said dielectric layer with at least oneacid solution having a concentration of from about 50% to about 100%phosphoric acid.
 12. A method for forming, from a silicon substrate, asemiconductor device bearing at least one isolation area and at leastone active area, comprising: providing a substrate; forming a layercomprising silicon nitride on a region of said substrate where the atleast one active area is to be located; forming an oxide on at least anuppermost surface of at least one region of said substrate exposedlaterally beyond said layer to form the at least one isolation area,silicon underlying said layer remaining substantially unoxidized;contacting surfaces of the at least one isolation area and said layerwith an acid solution comprising phosphoric acid at a first temperature,said acid solution at said first temperature exhibiting a positive etchselectivity for silicon oxide over silicon nitride; and graduallylowering a temperature of said acid solution to a second temperature,said acid solution at said second temperature exhibiting a positive etchselectivity for silicon nitride over at least one material of anadjacent layer or structure.
 13. The method according to claim 12,wherein said forming said oxide comprises thermally oxidizing said atleast one region of said substrate.
 14. The method according to claim12, wherein said forming said oxide comprises forming at least one of aBPSG oxide, a silane oxide, a TEOS oxide, an LPTEOS oxide, a PETEOSoxide, and an HDPTEOS oxide.
 15. The method according to claim 12,wherein said forming said layer comprises forming said layer by athermal nitridation technique.
 16. The method according to claim 12,wherein said forming said layer comprises forming at least one of a CVDnitride, an HTCVD nitride, a PECVD nitride, and an LPCVD nitride. 17.The method according to claim 12, further comprising forming a pad oxideprior to said forming said layer, said layer substantially covering saidpad oxide.
 18. The method according to claim 12, wherein said contactingis effected with said first temperature being greater than about 165° C.19. The method according to claim 12, wherein said contacting iseffected with said first temperature being about 165° C. to about 220°C.
 20. The method according to claim 12, wherein said contacting iseffected with said first temperature being about 175° C.
 21. The methodaccording to claim 12, wherein said contacting is effected with saidsecond temperature being less than about 165° C.
 22. The methodaccording to claim 12, wherein said contacting is effected with saidsecond temperature being about 145° C. to about 165° C.
 23. The methodaccording to claim 12, wherein said contacting is effected with saidsecond temperature being about 155° C.
 24. The method according to claim12, wherein said contacting comprises contacting said surface with atleast one acid solution having a concentration of from about 50% toabout 100% phosphoric acid.
 25. The method according to claim 12,wherein said gradually lowering comprises gradually lowering said acidsolution to said second temperature to impart said acid solution with apositive etch selectivity for silicon nitride over silicon oxide. 26.The method according to claim 25, wherein said gradually loweringfurther comprises lowering said acid solution to said second temperatureto impart said acid solution with a positive etch selectivity forsilicon nitride over silicon.